S. Tan, Y. Miao, M. Palm, J. Rodrigues, P. Andreani, “A continuous-time delta-sigma ADC with integrated digital background calibration,” Analog Integrated Circuits and Signal Processing, vol. 89, no. 2, pp. 273–282, Nov. 2016.
X. Liu, A. Nejdel, M. Palm, L. Sundström, M. Törmänen, H. Sjöland, P. Andreani, "A 65 nm CMOS Wideband Radio Receiver with ∆Σ-based A/D-Converting Channel-Select Filters," IEEE Journal of Solid-State Circuits, vol. 51, no. 7, pp. 1566-1578, Jul. 2016.
M. Andersson, M. Anderson, L. Sundström, S. Mattisson, and P. Andreani, "A Filtering ∆Σ ADC for LTE and Beyond," IEEE Journal of Solid-State Circuits, vol. 49, no. 7, pp. 1535-1547, Jul. 2014.
M. Andersson, L. Sundström, M. Anderson, and P. Andreani, "Theory and design of a CT ∆Σ modulator with low sensitivity to loop-delay variations," Analog Integrated Circuits and Signal Processing, vol. 76, no. 3, pp. 353–366, Sep. 2013.
M. Palm, D. Mastantuono, C. Jansson, E. Backenius, N. Ivanisevic, M. Normark, P. Harikumar, M. Yee, A. Leidenhed, R. Strandberg, S. Sharma, H. Ghaedrahmati, M. Anderson, P. Nygren, P. Sjögren, E. Säll, R. Hägglund, L. Sundström, "A 12/16 GSps Time-Interleaved Pipelined-SAR ADC with Temperature Robust Performance at 0.75V Supply in 7nm FinFET Technology," Proc. of IEEE ESSCIRC, Lisbon, Portugal, 2023, pp. 333-336.
S. Ek, P. Karlsson, A. Kämpe, R. Strandberg, A. Tharayil Narayanan, M. Anderson, H. Dafallah, M. Daghbashyan, T. Ghanavati Nejad, R. Hägglund, N. Ivanisevic, R. Nilsson, P. Nygren, M. Palm, E. Säll, S. Tao, M. Yee, L. Sundström, "A Bang-Bang Digital PLL Covering 11.1-14.3 GHz and 14.7-18.7 GHz with sub-40 fs RMS Jitter in 7 nm FinFET Technology," Proc. of IEEE ESSCIRC, Milan, Italy, 2022, pp. 237-240.
S. Tan, M. Palm, D. Mastantuono, R. Strandberg, L. Sundström, S. Mattisson and P. Andreani, "A Design Method to Minimize the Impact of Bit Conversion Errors in SAR ADCs," 2020 IEEE Nordic Circuits and Systems Conference (NorCAS), 2020, pp. 1-6.
S. Tan, D. Mastantuono, R. Strandberg, L. Sundström, P. Andreani and M. Palm, "A 10-Bit Split-Capacitor SAR ADC with DAC Imbalance Estimation and Calibration," IEEE International Symposium on Circuits and Systems (ISCAS), 2020, pp. 1-5.
S. Tan, L. Sundström, M. Palm, S. Mattisson and P. Andreani, "A 5 GHz CT Δ∑ ADC with 250 MHz Signal Bandwidth in 28 nm-FDSOI CMOS," IEEE Nordic Circuits and Systems Conference (NORCAS), 2019, pp. 1-4.
M. Palm, D. Mastantuono, R. Strandberg, L. Sundström, S. Mattisson, ”A 12b, 1 GSps TI pipelined-SAR converter with 65 dB SFDR through buffer linearization and gain mismatch correction in 28nm FD-SOI,” Proc. of IEEE ESSCIRC, Leuven, Belgium, Sep. 11-14 2017, pp. 179-180.
S. Tan, Y. Miao, M. Palm, J. Rodrigues, P. Andreani, "Digital background calibration in continuous-time delta-sigma analog to digital converters," Proc. of IEEE NORCAS, Oslo, Norway, Oct. 26-28 2015, pp. 1-4.
A. Nejdel, X. Liu, M. Palm, L. Sundström, M. Törmänen, H. Sjöland, P. Andreani, "A 0.6-3.0 GHz 65 nm CMOS Radio Receiver with ∆Σ-based A/D-Converting Channel-Select Filters," Proc. of IEEE ESSCIRC, Graz, Austria, Sep. 14-18 2015, pp. 299-302.
X. Liu, M. Andersson, M. Anderson, L. Sundström, P. Andreani, "An 11mW continuous time delta-Sigma modulator with 20 MHz bandwidth in 65nm CMOS," in Proc. of IEEE International Symposium on Circuits and Systems, Melbourne, Australia, Jun. 1-5 2014, pp. 2337-2340.
S. Yan, M. Andersson, H. Sjöland, "A 31.25/125MSps Continuous-Time Delta-Sigma ADC with 64/59dB SNDR in 130nm CMOS," in Proc. of IEEE NORCHIP, Vilnius, Lithuania, Nov. 11-12 2013. pp. 1-4.
M. Andersson, M. Anderson, L. Sundström, S. Mattisson, and P. Andreani, "A 9MHz Filtering ADC with Additional 2nd-order ∆Σ Modulator Noise Suppression," IEEE ESSCIRC 2013, Bucharest, Romania, Sep. 16–20 2013, pp. 323–326.
M. Andersson, M. Anderson, L. Sundström, and P. Andreani, "A 7.5 mW 9 MHz CT ∆Σ Modulator in 65 nm CMOS With 69 dB SNDR and Reduced Sensitivity to Loop Delay Variations," in Proc. of IEEE A-SSCC, Kobe, Japan, Nov. 12–14 2012, pp. 245–248.
M. Anderson, R. Strandberg, S. Ek, L. Wilhelmsson, L. Sundström, M. Andersson, I. ud Din, J. Svensson, T. Olsson, and D. Eckerbert, "A 4.75 - 34.75 MHz Digitally Tunable Active-RC LPF for >60 dB Mean RX IRR in 65 nm CMOS," in Proc. of 38th IEEE ESSCIRC 2012, Bordeaux, France, Nov. 17–21 2012, pp. 470–473.
L. Sundström, M. Anderson, M. Andersson, and P. Andreani, "Harmonic Rejection Mixer at ADC Input for Complex IF Dual Carrier Receiver Architecture," in RFIC, Montreal, Canada, Jun. 17–19 2012, pp. 265–268.
M. Andersson, M. Anderson, P. Andreani, and L. Sundström, "Impact of MOS threshold-voltage mismatch in current-steering DACs for CT ∆Σ modulators," in Proc. of IEEE International Symposium on Circuits and Systems, Paris, France, May 30–Jun. 2 2010, pp. 4021–4024.
M. Andersson, M. Anderson, L. Sundström, and P. Andreani , "A CT ∆Σ ADC for LTE in 65 nm CMOS with 69dB SNDR and Low Sensitivity to Loop Delay Variations," Swedish System-on-Chip Conference SSoCC 2013, Varberg, Sweden, May. 6-7, 2013.
M. Andersson, M. Anderson, P. Andreani, and L. Sundström, "Mismatch of switch transistors in current-steering DACs for CT ∆Σ Modulators," Swedish System-on-Chip Conference SSoCC 2011, Varberg, Sweden, May. 2, 2011.
M. Andersson, "Continuous-Time Delta-Sigma Modulators for Wireless Communication," Vol. 55, ISSN 1654-790X, Department of Electrical and Information Technology, Faculty of Engineering, LTH, Lund University, 2014.
Keywords:
CMOS, delta-sigma modulator (DSM), analog-to-digital converter, signal transfer function (STF), noise transfer function (NTF), lowpass, filtering ADC, non return-to-zero (NRZ), RZ, loopdelay, nyquist, time-interleaving, SAR, pipeline, data converter.